The Mobile Industry Processor Interface Display Serial Interface (hereinafter, MIPI DSI) protocol standard is related to a high-speed serial interface between a MIPI host and a display panel. Two modes are supported in MIPI DSI, namely, command mode and video mode.
FIG. 1A is a schematic diagram illustrating a display device operating in a video mode. The display device 10a includes a MIPI host 11a and a display panel 13a. The MIPI host 11a includes a frame buffer 111a. The display panel 13a includes a display driving circuit 131a and a panel device 133a, which are electrically connected to each other.
The display driving circuit 131a further includes an internal clock circuit 1311a and a function circuit 1313a capable of providing interface control function of the display device 10a. The function circuit 1313a is electrically connected to the MIPI host 11a, the internal clock circuit 1311a, and the panel device 133a. 
For the display device 10a operating in the video mode, the MIPI host 11a and the function circuit 1313a communicate with each other through display data DAT and display commands CMD. Through the display commands CMD, the MIPI host 11a transmits timing related information, for example, the vertical sync signal, the horizontal sync signal and so forth, to the function circuit 1313a. 
The function circuit 1313a operates based on an internal clock signal CLKint generated and provided by the internal clock circuit 1311a. The internal clock signal CLKint may be easily affected by environment. In the video mode, the display commands CMD originating from the MIPI host 11a includes timing related information. Therefore, the function circuit 1313a can determine whether the actual frequency of the internal clock signal Fint is matched to a standard frequency of the internal clock signal Fint_std by referring the timing information from the MIPI host 11a. 
FIG. 1B is a schematic diagram illustrating a display device operating in a command mode. The display device 10b includes a MIPI host 11b and a display panel 13b. Unlike the MIPI host 11a in FIG. 1A, the MIPI host 11b does not include a frame buffer. The display panel 13b includes a display driving circuit 131b and a smart panel 133b, which are electrically connected to each other. In FIG. 1B, the smart panel 133b further includes a frame buffer 1331b and a panel device 1333b. 
Similar to FIG. 1A, the display driving circuit 131b further includes an internal clock circuit 1311b and a function circuit 1313b. The function circuit 1313b is electrically connected to the MIPI host 11a, the internal clock circuit 1311a, and the smart panel 133b. In the command mode, the frame buffer 1331b is not placed in the MIPI host 11b but the smart panel 133b. Unlike the video mode, MIPI host 11a transmits only display refresh signal Sdr to the function circuit 1313b in the command mode. However, the display refresh signal Sdr excludes the timing information and the function circuit 1313b does not have reference for determining frequency precision of the internal clock signal CLKint.
According to MIPI DI standard, the function circuit is required to operate based on a central frequency, and tolerance range is relatively small, for example, +/−1%˜+/−2%. However, regardless the video mode and/or the command mode, frequency of the internal clock signal Fint may drift because of temperature change or process variation. Whereas, as shown in FIG. 1B, the internal clock signal CLKint cannot be adjusted when the display device 10b operates in the command mode. Therefore, a mechanism for determining and calibrating frequency of the internal clock signal Fint in the command mode is necessary.